Statistical Estimation of the Switching Activity in Digital Circuits

Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these problems are directly related to the extent of circuit switching activity. The average number of transitions per second at a circuit node is a measure of switching activity that has been called the transition density. This paper presents a statistical simulation technique to estimate individual node transition densities. The strength of this approach is that the desired accuracy and con dence can be speci ed up-front by the user. Another key feature is the classi cation of nodes into two categories: regularand low-density nodes. Regulardensity nodes are certi ed with user-speci ed percentage error and con dence levels. Low-density nodes are certi ed with an absolute error, with the same con dence. This speeds convergence while sacri cing percentage accuracy only on nodes which contribute little to power dissipation and have few reliability problems.